Analog Devices-1297

►

ANALOG
DEVICES

CMOS

IxP-Compatible 8-Bit ADC

AD7574

FEATURES
8-Bit Resolution

No Missed Codes over Full Temperature Range

Fast Conversion Time: 15/js

Interfaces to fiP like RAM, ROM or Slow - Memory

Low Power Dissipation: 30mW

Ratiometric Capability

Single +5V Supply

Low Cost

Internal Comparator and Clock Oscillator

GENERAL DESCRIPTION

AD7574 is a low-cost, 8-bit (lP compatible ADC which uses
the successive-approximations technique to provide a con-
version time of 15fis-

Designed to be operated as a memory mapped input device,
the AD7574 can be interfaced like static RAM, ROM, or slow
memory. Its CS (decoded device address) and RD
(READ/WRITE control) inputs are available in all //P memory
systems. These two inputs control all ADC operations such as
starting conversion or reading data. The ADC output data bits
use three-state logic, allowing direct connection to the //P data
bus or system input port.

Internal clock, +5V operation, on-board comparator and
interface logic, as well as low power dissipation (30mW) and
fast conversion time make the AD7574 ideal for most ADC/juP
interface applications. Small size (18-pin DIP) and monolithic
reliability will find wide use in avionics, instrumentation, and
process automation applications.

FUNCTIONAL BLOCK DIAGRAM

Vdd V flEF
O ®-

PIN CONFIGURATION

vdd

LT

V R £F

E

B OFS

d

*IN

n

A GND

LI

DB ? (MSB)

d

DB 6

LI

DB b

LI

DB„

E

H1 d gnd

TT| CLK

Til cs

in rd

77] BUSY
751 DBn ILSBI

"TIIdb,
T7| db 2

TOP VIEW
(NOT TO SCALE)

ORDERING GUIDE

Differential

Temperature

Nonlinearity

Package

Model

Range

(LSB)

Option*

AD7574JN

0°C to +70°C

±7/8 max

N-24

AD7574KN

0°C to +70°C

±3/4 max'

N-24

AD7574AQ

-25°C to +85°C

±7/8 max

Q-24

AD7574BQ

-25°C to +85°C

±3/4 max

Q-24

AD7574SQ

-55°Cto +125°C

±7/8 max

Q-24

AD7574TQ

-55°C to +125°C

±3/4 max

Q-24

*N = Plastic DIP; Q = Cerdip.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577

Telex: 924491 Cable: ANALOG NORWOODMASS

AD7574— SPECIFICATIONS

DC SPECIFICATIONS (Vqq = +5V, V REF = -10V, Unipolar Configuration, R CLK = 180kil, C CLK = 100pF, unless otherwise noted)

Limits

Parameter

T A = +25°C

T mi „, T m J

Units

Conditions/Comments

ACCURACY

Resolution

S

8

Bits

Relative Accuracy Error

J, A, S Versions

±3/4

±3/4

LSB max

Relative Accuracy and Differential Nonlinearity are measured

K, B, T Versions

± 1/2

-+- 1 n

LSB max

dynamically using the external clock circuit of Figure 7b.

Differential Nonlinearity

Clock frequency is 500kHz (conversion time 15u.s).

J, A, S Versions

+ 7/8

±7/8

LSB max

K, B, T Versions

±3/4

±3/4

LSB max

Full Scale Error (Gain Error)

Full Scale Error is measured after calibrating out offset error. See

J, A, S Versions

±5

±6.5

LSB max

Figure 8a and associated calibration procedure for offset. Max Full

K, B, T Versions

±3

±4.5

LSB max

Scale change from +25°C to T min or T^ is ±2LSB.

Offset Error 2

J, A, S Versions

±60

±80

mV max

Maximum Offset change from +25°C to T min or T mal is ±20mV.

K, B, T Versions

±30

±50

mV max

Mismatch Between B OFS (Pin 3)

and A IN (Pin 4) Resistances 3

±1.5

±1.5

% max

ANALOG INPUTS

Input Resistance

At V MF (Pin 2)

5/10/15

5/10/15

kfl min/typ/max

At B OFS (Pin 3)

10/20/30

10/20/30

kfl min/typ/max

At A IN (Pin 4)

10/20/30

10/20/30

kfl min/typ/max

Vref (f° r Specified Performance)

-10

-10

V

±5% for specified transfer accuracy.

V REF Range 4

-5 to -15

-5 to -15

V

Degraded transfer accuracy.

Nominal Analog Input Range

Unipolar Mode

to +

VrefI

V

Bipolar Mode

"|V REF | tc

+|v bef |

V

LOGIC INPUTS

RD (Pin 15), CS (Pin 16)

V INH Logic HIGH Input Voltage

+3.0

+3.0

V min

V INL Logic LOW input Voltage

+0.8

+0.8

V max

I [N Input Current

1

10

u.A max

v IN = ov, V DD

C IN Input Capacitance 7

5

5

pF max

CLK (Pin 17)

V INH Logic HIGH Input Voltage

+3.0

+ 3.0

V min

V mL Logic LOW Input Voltage

+0.4

+0.4

V max

Ijnh Logic HIGH Input Current

+2

+2

mA max

During Conversion: V IN(CLK) > V INH(CLK)

I mL Logic LOW Input Current

1

10

uA max

During Conversion V IN(CLK) < V 1NL(CLK)

(see circuit of Figure 7b if external clock operation is required).

LOGIC OUTPUTS

BUSY (Pin 14), DB 7 to DB (Pins 6-13)

V OH Output HIGH Voltage

+4.0

+4.0

V min

^source = 40^A

V OL Output LOW Voltage

+0.4

+0.8

V max

Isink = L6mA

Ilkg DI3 7 to DB Floating Stage Leakage

1

10

u,A max

v OUT ~ " v or V DD

Floating State Output Capacitance

(DB 7 to DB ) 5

7

7

pF max

Output Code

Unipo

ar Binary, Off

set Binary

See Figures 8a, 9a, 10a, and 8b, 9b, 10b.

POWER REQUIREMENTS

v DD

+ 5

+5

V

±5% for specified performance.

I DD (STANDBY)

5

5

mA max

A IN = 0V, ADC in RESET condition.

Iref

V REF divided by 5kfl

max

Conversion complete, prior to RESET.

NOTES

'Temperature ranges as follows: J, K, Versions, 0°C to +70°C; A, B.Versions, -25°C to +85°C; S, T Versions; -55°C to +125°C.
2 Typical offset temperature coefficient is ±150|aV/°C.

3 Rbofs^ain mismatch causes transfer function rotation about positive Full Scale. The effect is an offset and a gain term when using the circuit of Figure 9a.
*Typical value, not guaranteed or subject to test,
guaranteed but not tested.
Specifications subject to change without notice.

CAUTION

ESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.

-2-

REV.A

AC SPECIFICATIONS (V D D = +5 V, c CLK = I Q OpF, R ELK = 18 0M1 unless otherwise noted)

Symbol

Specification

STATIC RAM INTERFACEMODE (See Figure 1 and Table I)

*cs

tws

*BSR
tfiSCS
*RAD

l RHCS

Preset
^convert

^CONVERT

CS Pulse Width Requirement

RD to CS Se tup Time

CS to BUSY Propagation Delay

BUSY to RD Setup Time
BUSY to CS Setup Time
Data Access Time

Data Hold Time

CS to RD Hold Time

Reset Time Requirement

Conversion Time

Using Internal Clock Oscillator

Conversion Time

Using External Clock

ROM INTERFACE MODE (See Figure 2 and Table II)

*RAD

Irhd
Wbpd

Data Access Time
Data Hold Time

RD HIGH to BUSY

Propag ati on D elay

BUSY to RD LOW Setup Time

Conversion Time

Using Internal Clock Oscillator

Limit at

Limit at

Limit at

T A = +25°C

1"a = T min

T.\ = T maJt

100ns min

150ns min

150ns min

min

min

min

90ns typ

70ns typ

150ns typ

120ns max

120ns max

180ns max

120ns type

100ns typ

180ns typ

150ns max

150ns max

200ns max

min

min

min

min

min

min

120ns typ

100ns typ

180ns typ

150ns max

150ns max

220ns max

240ns typ

220ns typ

300ns typ

300ns max

300ns max

400ns max

80ns typ

40ns typ

120ns typ

50ns min

30ns min

80ns min

120ns max

80ns max

180ns max

250ns max

200 ns max

500ns max

3u.s min

3jjls min

-Vs min

See Typical Data of Figure 7a

15u,s

15u.s

15jls

400ns typ
L5ja,s

Same as RAM Mode
Same as RAM Mode
350ns typ
1.0u.s

lu-s typ
2.0u.s
HIGH, but must not

Conditions

BUSY Load = 20pF

BUSY Load = lOOpF

DB -DB 7 Load = lOOpF
DB -DB 7 Load = lOOpF

Circuit of Figure 7b

BUSY Load = 20 pF

RD can go LOW prio r to BU SY
return HIGH until = BUSY HIGH. See Table II.
See Typical data of Figure 7a. Add 2\ls to
data shown in Figure 7a for ROM Mode

SLOW - MEMORY INTERFAC E MOD E (See Figure 3 and Table III)

*CBFD

Preset

l RAD

'rhd

tcONVERT

CS to BUSY Propagation Delay
Reset Time Requirement
Data Access Time
Data Hold Time
Conversion Time

Same as RAM Mode
Same as RAM Mode
Same as RAM Mode
Same as RAM Mode
Same as RAM Mode

ABSOLUTE MAXIMUM RATINGS*

V DD to Ag ND 0V, +7.0V

V DD to D GND 0V, +7.0V

Ag ND to D GND -0.3V, V DD

Digital Input Voltage to D GND (Pins 15 and 16) .... -0.3V, + 15.0V

Digital Output Voltage to D GND (Pins 6-14) -0.3V, V DD

CLK Input Voltage (Pin 17) toD GND -0.3V, V DD

V^ (Pin 2) ±20V

V BOFS (Pin 3) ±20V

V^ (Pin 4) ±20V

Operating Temperature Range
Commercial (J, K Versions) 0°C to +70°C

Industrial (A, B Versions) -25°C to + 85°C

Extended (S, T Versions) -55°C to +150°C

Storage Temperature Range -65°C to +150°C

Lead Temperature (soldering, 10 sees) +300°CV

Power Dissipation (Package)
Plastic (Suffix N)

to + 70°C 670mW

Derate above +70°C by 8.3mW/°C

Cerdip (Suffix Q)

to +75°C 450mW

Derate above +75°C by 6mW/°C

♦Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
at or above this specification is not implied. Exposure to above maximum rating conditions for extended periods may affect device reliability.

TERMINOLOGY

RESOLUTION: Resolution is a measure of the nominal analog
change required for a 1-bit change in the A/D converter's digital
output. While normally expressed in a number of bits, the analog
resolution of an n-bit unipolar A/D converter is (2 n ) V REF ).
Thus, the AD7574, an 8-bit A/D converter, can resolve analog
voltages as small as (1/256) (V REF ) when operated in a unipolar
mode. When operated in a bipolar mode, the resolution is (1/128)
(Vrep). Resolution does not imply accuracy. Usable resolution is
limited by the differential nonlinearity of the A/D converter.

RELATIVE ACCURACY: Relative accuracy is the deviation of
the ADC's actual code transition points from a straight line

drawn between the devices' measured zero and measured full
scale transition points. Relative accuracy, therefore, is a measure
of code position.

DIFFERENTIAL NONLINEARITY: Differential nonlinearity
in an ADC is a measure of the size of an anlog voltage range
associated with any digitial output code. As such, differential
nonlinearity specifies code width (usable resolution). An ADC
with a specified differential nonlinearity of ±n bits will exhibit
codes ranging in width from 1LSB — n LSB to 1LSB +n LSB.
A specified differential nonlinearity of less than ± 1LSB guaran-
tees no-missing-codes operation.

REV. A

-3-

AD7574

TIMING & CONTROL OF THE AD7574
STATIC RAM INTERFACE MODE

Table I and Figure 1 show the truth table and timing require-
ments for AD7574 operation as a static RAM.

A convert start is initiated by executing a memory WRITE
instruction to the address location occupied by the AD7574
(once conversion has started, subsequent memory WRITES
have no effect). A data READ is performed by executing a
memory READ instruction to the AD7574 address location.

BUSY must be HIGH before a data READ is attempted, i.e.
the total delay between a convert start and a data READ must
be at least as great as the AD7574 conversion time. The delay

can be generated by inserting NOP instructions (or other
program instructions) between the WRITE (start convert) and
READ (read data) operations. Once BUSY is HIGH (conver-
sion complete), a data READ is performed by executing a
memory READ instruction to the address location occupied
by the AD7574. The data readout is destructive, i.e. when RD
returns HIGH, the converter is internally reset.

The RAM interface mode uses distinctly different commands
to start conversion (memory WRITE) or read the data (memory
READ). This is in contrast to the ROM mode where a memory
READ causes a data READ and a conversion restart.

Table I. Truth Table, Static RAM Mode

IMEMORYWRITEl NOP OR OTHER
TOAD7574 INS TRUCT IONS
I ADDRESS I UNTIL BUSY IS HIGH

I MEMORY WRITE

TO AD7574
I ADDRESS

\ r

'4

De 7 -DBo ^
(PINS 6-13)

V

AD7574 INPUTS

AD7574 OUTPUTS

CS

RD

BUSY

db 7 -db

AD7574 OPERATION

L

H

H

HIGH L

WRITE CYCLE (START CONVERT)

L

II

HIGH Z ~* DATA

READ CYCLE (DATA READ)

L

_r

H

DATA -+ HIGH Z

RESET CONVERTER

H

X 1

X

HIGH Z

NOT SELECTED

L

H

L

HIGH Z

NO EFFECT, CONVERTER BUSY

L

L

HIGH Z

NO EFFECT, CONVERTER BUSY

L

L

HIGH Z

NOT ALLOWED, CAUSES

INCORRECT CONVERSION

Note 1 : If RD goes LOW to HIGH when CS is LOW, the ADC is
internally reset. RD has no effect while CS is HIGH.
See application hint No. 1.

Figure 1. Static RAM Mode Timing Diagram

ROM INTERFACE MODE

Table II and Figure 2 show the truth table and timing require-
ments for interfacing the AD7574 like Read Only Memory.
CS is held LOW and converter operation is controlled by the
RD input. The AD7574 RD input is derived from the decoded
device address. MEMRD should be used to enable the address
decoder in 8080 systems. VMA should be used to enable the
address decoder in 6800 systems. A data READ is initiated by
executing a memory READ instruction to the AD7574 address
location. The converter is automatically restarted when RD

I MEMORY READI MEMORY READ
TOA07574 NOP OR OTHER INSTRUCTIONS TOAD7S74
ADDRESS I ADDRESS

returns HIGH. As in the RAM mode, attempting a data READ
before BUSY is HIGH will result in incorrect data being read.

The advantage of the ROM mode is its simplicity. The major
disadvantage is that the data obtained is relatively poorly
defined in time inasmuch as executing a data READ auto-
matically starts a new conversion. This problem can be over-
come by executing two READs separated by NO-OPS (or
other program instructions) and using only the data obtained
from the second READ.

Table II. Truth Table, ROM Mode

AD7S74 INPUTS

AD7574 OUTPUTS

CS

RD

BUSY

DB 7 -DB

AD7574 OPERATION

L

H

HIGH Z ~* DATA

DATA READ

L

DATA-* HIGH Z

RESET AND

START NEW CONVERSION

L

L

HIGH Z

NO EFFECT, CONVERTER BUSY

L

L

HIGH Z

NOT ALLOWED, CAUSES

INCORRECT CONVERSION

Figure 2. ROM Mode Timing Diagram (CS Held LOW)

SLOW-MEMORY INTERFACE MODE

Table III and Figure 3 show the truth table and timing require-
ments for interfacing the AD7574 as a slow -memory. This
mode is intended for use with processors which can be forced
into a WAIT state for at least 12/is (such as the 8080, 8085
and SC/MP). The major advantage of this mode is that it
allows the fiP to start conversion, WAIT, and then READ data
with a single READ instruction.

In the slow -memory mode, CS and RD are tied together. It is
suggested that the system ALE signal (8085 system) or SYNC
signal (8080 system) be used to latch the address. The decoded

device address is subsequently used to drive the AD7574 CS
and RD inputs. BUSY is connected to the microprocessor
READY input.

When the AD7574 is NOT addressed, the CS and RD inputs
are HIGH. Conversion is initiated by executing a memory
READ to the AD7574 address. BUSY subsequently goes LOW
(forcing the juP READY input LOW) placin g the jltP in a WAIT
state. When conversion is complete (BUSY is HIGH) the juP
completes the memory READ.

Do not attempt to perform a memory WRITE in this mode,
since three -state bus conflicts will arise.

-4-

REV. A

AD7574

Figure 3. Slow Memory Mode Timing Diagram
(CSand RD Tied Together)

Table III. Truth Table, Slow Memory Mode

AD7S74 INPUTS

AD7S74 OUTPUTS

CS & RD

BUSY

DB 7 -DB

AD7574 OPERATION

H

H

HIGH 7,

NOT SliLECTbD

H ~* L

HIGH Z

START CONVERSION

L

L

HICII Z

CONVERSION IN PROGRESS,

flP IN WAIT STATE

L

IIICII Z ~* DATA

CONVERSION COMPLETE,

fJP READS DATA

II

DATA ^HICH Z

CONVERTER RESET

AND DESELECTED

H

H

HIGH Z

NOT SELECTED

GENERAL CIRCUIT INFORMATION

BASIC CIRCUIT DESCRIPTION

The AD7574 uses the successive approximations technique to
provide an 8 -bit parallel digital output. The control logic was
designed to provide easy interface to most microprocessors.
Most applications require only passive clock components (R &
C), a -10V reference, and +5V power.

DB, - DB„ PM~
DATA OUT

Figure 4. AD 75 74 Functional Diagram

Each successively smaller bit is tried and compared to Ajn in
this manner until the least significant bit (LSB) decision has
been made. At this time BUSY goes HIGH (conversion is com-
plete) indicating the successive approximation register contains
a valid representation of the analog input. The RD control (see
the previous page for details) can then be exercised to activate
the three-state buffers, placing data on the DBq - DB7 data
output pins. RD returning HIGH causes the clock oscillator to
run for 1 cycle, providing an internal ADC reset (i.e. the SAR
is loaded with code 10000000).

DAC CIRCUIT DETAILS

The current weighting D/A converter is a precision multiplying
DAC. Figure 5 shows the functional diagram of the DAC as
used in the AD7574. It consists of a precision Silicon Chrom-
ium thin film R/2R ladder network and 8 N - channel MOS-
FET switches operated in single - pole - double - throw.

The currents in each 2R shunt arm are binarily weighted, i.e.
the current in the MSB arm is V RE p divided by 2R, in the
second arm is Vj^gp divided by 4R, etc. Depending on the
DAC logic input (A/D output) from the successive approx-
imation register, the current in the individual shunt arms is
steered either to Aqj^d or to the comparator summing point.

Figure 4 shows the AD7574 functional diagram. Upon receipt
of a start command either via the CS or RD pins, BUSY goes
low indicating conversion is in progress. Successive bits,
starting with the most significant bit (MSB) are applied to
the input of a DAC. The comparator determines whether the
addition of each successive bit causes the DAC output to be
greater than or less than the analog input, A m . If the sum of
the DAC bits is less than A[n, the trial bit is left ON, and the
next smaller bit is tried. If the sum is greater than Ai N , the
trial bit is turned OFF and the next smaller bit is tried.

Figure 5. D/A Converter As Used In AD7574

REV. A

-5-

AD7574

OPERATING THE AD7574

APPLICATION HINTS

1. TIMING & CONTROL

In the AD7574 when a conversion is finished the fresh data

must be read before a new conversion can be started.

Failure to observe the timing restrictions of Figures 1, 2 or 3 may

cause the AD7574 to change interface modes. For example, in the

RAM mode, holding CS LOW too long after RD goes HIGH will

cause a new convert start (i.e. the converter moved into the ROM

mode).

2. LOGIC DEGLITCHING IN uP APPLICATIONS

Unspecified states on the address bus (due to different rise and fall
times on the address bus) can cause glitches at the AD7574 CS or
RD terminals. These glitches can cause unwanted convert starts,
reads, or resets. The best way to avoid glitches is to gate the address
decoding logic with RD or WR (8080) or VMA (6800) when in the
ROM or RAM mode. When in the slow - memory mode, the ALE
(8085) or SYNC (8080) signal should be used to latch the address.

3. INPUT LOADING AT V REF , A IN AND B OFS

To prevent loading errors due to the finite input resistance at the
Vrep, Ajn or BqfS P' ns i ' ow impedance driving sources must be
used (i.e. op amp buffers or low output - Z reference).

4. RATIOMETRIC OPERATION

Ratiometric performance is inherent to A/D converters such as the
AD7574 which use a multiplying DAC weighting network. However,

the user should recognize that comparator limitations such as offset
voltage, input noise and gain will cause degradation of the transfer
characteristics when operating with reference voltages less than
-10V in magnitude.

5. OFFSET CORRECTION

Offset error in the transfer characteristic can be trimmed by off-
setting the buffer amplifier which drives the AD7574 Ajn pin (pin
4). This can be done either by summing a cancellation current into
the amplifier's summing junction, or by tapping a voltage divider
which sits between Vjjd and Vref anc * a PP'y' n g tne ta P voltage to
the amplifier's positive input (an example of a resistive tap offset
adjust is shown in Figure 10a where Rg, Ro and Rjo can be used to
offset the ADC).

6. ANALOG AND DIGITAL GROUND

It is recommended that AgND and DfjND be connected locally to
prevent the possibility of injecting noise into the AD7574. In
systems where the AqnD'DgnD intertie is not local, connect
back - to - back diodes (IN914 or equivalent) between the AD7574
AgND » ntl D GND P' ns -

7. INITIALIZATION AFTER POWER -UP

Execute a memory READ to the AD7574 address location, and
subsequently ignore the data. The AD7574 is internally reset when
reading out data, i.e. the data readout is destructive.

CLOCK OSCILLATOR

The AD7574 has an internal asynchronous clock oscillator
which starts upon receipt of a convert start command, and
ceases oscillating when conversion is complete.

The clock oscillator requires an external R and C as shown in
Figure 6. Nominal conversion times versus Rclk and Qxk i s
shown in Figure 7a. The curves shown in Figure 7a are applic-
able when operating in the RAM or slow - memory interface
modes. When operating in the ROM interface mode, add 2/xs
to the typical conversion time values shown.

The AD7574 is guaranteed to provide transfer accuracy to
published specifications for conversion times down to 15/Lts,
as indicated by the unshaded region of Figure 7a. Conversion
times faster than 15/is can cause transfer accuracy degradation.

OPERATION WITH EXTERNAL CLOCK

For applications requiring a conversion time close to or equal
to 15/is, an external clock is recommended. Using an external
clock precludes the possibility of converting faster than 15/is
(which can cause transfer accuracy degradation) due to temp-
erature drift — as may be the case when using the internal
clock oscillator.

Figure 7b shows how the external clock must be connected.
The BUSY output of the AD7574 is connected to the three-
state enable input of a 74125 three-state buffer. Rj is used as
a pullup, and can be between 6kf2 and 100kf2. A 500kHz
clock will provide a conversion time of 1 5(is.

The external clock should be used only in the static - RAM or
slow -memory interface mode, and not in the ROM mode.

Timing constraints for external clock operation are as follows:

STATIC RAM MODE _

1. When initiating a conversion, CS should go LOW on a pos-
itive clock edge to provide optimum settling time for the
MSB.

2. A data READ can be initiated any time after BUSY = 1.

SLOW-MEMORY MODE _

1. When initiating a conversion, CS and RD should go LOW

on a positive clock edge to provide optimum settling time
for the MSB.

V DD H5VI

«CLK

D GND

Figure 6. Connecting RqlK ano> ^CLK ^° Oscillator

1 1

"CLK ■ 2

00k!l.C CL

K-IOOpF

R CLK

= 125kS2,C

CLK " 'MP

F

WER

UOEDAf

£A

B :,: ;J-; : iJ;.:i;

TRANSFER ACCURACY

.: :fl CLf

= 75k£!,C

:lk ■ '°°i>

AMBIENT TEMPERATURE ( Celciu,}

Figure 7a. Typical Conversion Time vs. Temperature For
Different RqlK and C CLK (Applicable to RAM and Slow -
Memory Modes. For ROM Mode add 2fis to values shown)

max) r>c^

r thhe

Figure 7b. External Clock Operation (Static RAM
and Slow- Memory Mode)

-6-

REV. A

UNIPOLAR BINARY OPERATION

Figures 8a and 8b show the analog circuit connections and

typ i c al tr a nsfer ch a r a cteristic for unipol a r oper a tion . An

AD584 is used as the -10V reference.

Calibration is as follows:
OFFSET

Offset must be trimmed out in the signal conditioning cir-
cuitry used to drive the signal input terminals shown in Figure
8a. An example of an offset trim is shown in Figure 10a,
where Rg, R and Rjq comprise a simple voltage tap which is
applied to the amplifier's positive input.

SUPP LY RETURN

Note 1 : Ri and R2 can be omitted if
gain trim is not required

Figure 8a. AD7574 Unipolar (0V to +10V) Operation
(Output Code is Straight Binary)

AD7574

1. Apply -39.1mV (1 LSB) to the input of the buffer ampli-
fier used to drive Rj (i.e. +39.1mV at Rj).

2 . While perform ing continuous conversions, adjust the offset
potentiometer (described above) until DB7-DB1 are LOW
and the LSB (DB ) flickers.

GAIN (FULL SCALE)

Offset adjustment must be performed before gain adjustment.

1. Apply -9.961V to the input of the buffer amplifier used to
drive Rj (i.e. +9.961 V at R x ).

2. While performing continuous conversions, adjust trim pot
R 2 until DB7 -DBj are HIGH and the LSB (DB ) flickers.

□ MO 080 120 9.910 9 960 10.000

INPUT VOLTAGE, VOLTS

Note: Approximate bit weights are shown for illustration.

Nominal bit weight for a -10V reference is =s 39.1 mV

Figure 8b. Nominal Transfer Characteristic For Unipolar
Circuit of Figure 8a

BIPOLAR (OFFSET BINARY) OPERATION

Figures 9a and 9b illustrate the analog circuitry and transfer
characteristic for bipolar operation. Output coding is offset
binary. As in unipolar operation, offset correction can be per-
formed at the buffer amplifier used to drive the signal input
terminals of Figure 9a (Resistors Rg, R9 and R 10 in Figure
10a show how offset trim can be done at the buffer amplifier).

Calibration is as follows:

1. Adjust Rg and R7 for minimum resistance across the
potentiometers.

2. Apply +10.000V to the buffer amplifier used to drive the
signal input (i.e. -10.000V at R 6 ).

3. While performing continuous conversions, trim Rg or R7
(whichever required) until DB7 - DBj are LOW and the LSB
(DBq) flickers.

Note 1 : R1 and R2 can be omitted if
gain trim is not required

Figure 9a. AD7574 Bipolar (-10V to +10V) Operation
(Output Code is Offset Binary)

4. Apply 0V to the buffer amplifier used to drive the signal
input terminals.

5. Doing continuous conversions, trim the offset circuit of the
buffer amplifier until the ADC output code flickers
between 01111111 and 10000000.

6. Apply +10.000V to the input of the buffer amplifier
(i.e. -10.000V as applied to R ).

7. Doing continuous conversions, trim R 2 until DB7-DB1 are
LOW and the LSB (DB Q ) flickers.

8. Apply -9.922V to the input of the buffer amplifier (i.e.
+9. 922V at the input side of Rg).

9. If the ADC output code is not 11111110 ±1 bit, repeat the
calibration procedure.

OUTPUT

-40O -320 -240 -160 -80 +00 -1*0 .2*0 .110 .400
INPUT VOLTAGE, MILLIVOLTS

Note: Approximate bit weights are shown for illustration.
Nominal bit weight for ± 10V full scale is «s 78.1 mV

Figure 9b. Nominal Transfer Characteristic Around
Major Carry for Bipolar Circuit of Figure 9a

REV. A

-7-

AD7574

OPERATING THE AD7574

BIPOLAR (COMPLEMENTARY OFFSET
BINARY) OPER ATION

Figure 10a shows the analog connections For complementary
offset binary operation. The typical transfer characteristic is
shown in Figure 10b. In this bipolar mode, the ADC is fooled
into believing it is operated in a unipolar mode - i.e. the +10V
to -10V analog input is conditioned into a to +10V signal
range. R2 is the gain adjust, while R9 is the offset adjust.

Calibration is as follows (adjust offset before gain) :

OFFSET

1. Apply OV to the analog input shown in Figure 10a.

2. While performing continuous conversions, adjust Ro until
the converter output flickers between codes 01111111 and
10000000.

GAIN (FULL SCALE)

1. Apply -9.922V across the analog input terminals shown in
Figure 10a.

2. While performing continuous conversions, adjust R2 until
PB 7 - DBj are HIGH and the LSB (DB ) flickers between
HIGH and LOW.

10

00

If)

I

■o
in
o
10
O

SUPPLY RETURN 1

SUPPLY RETURN \

Notes:

1. R1 and R2 can be omitted if gain trim is not required

2. R8. R 9 and R 10 can ^ omitted if offset trim is not required

3. R6||R8ll R 10 = 5k ^- lf R 8. R 9 and R 10 not used ' make R 6 = 5kf2

Figure 10a. AD7574 Bipolar Operation (-10V to +10V)
(Output Code is Complementary Offset Binary)

OUTPUT

CODE
01111011

01111101
01111110

Note: Approximate bit weights are shown for illustration. Nominal
bit weight for ±10V full scale is as 78.1 mV

Figure 10b. Nominal Transfer Characteristic Around Major
Carry for Bipolar Circuit of Figure 10a

MECHANICAL INFORMATION

OUTLINE DIMENSIONS

Dimensions are shown in inches and (mm).

18 PIN PLASTIC DIP

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18 PIN CERAMIC DIP

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HI 1 h

.soatoio) 2.97 tios )

-MKOIS) 2.41 (MS)

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D

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DC
a.

Notes:

1. Lead no.1 identified by dot
or notch.

2. Dimensions in mm (in.).

3. Leads are solder plated KOVAR
or ALLOY 42.

Notes:

1 . Lead no. 1 identified by dot
or notch.

2. Leads will be either gold or tin
plated in accordance with
MIL-M-38510 requirements.

3. Cavity lid is electrically isolated.

-8-

REV. A